1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device.
Priority is claimed on Japanese Patent Application No. 2010-019659, filed Jan. 29, 2010, the content of which is incorporated herein by reference.
2. Description of the Related Art
Recently, with the miniaturization of semiconductor elements, the size of transistors has been reduced. The reduction in size of the transistors causes the short channel effect. In a case of a DRAM (Dynamic Random Access Memory), the channel lengths of transistors are reduced along with a reduction in the size of memory cells, thereby decreasing performance of the transistor, and therefore degrading retention and write characteristics of memory cells.
To solve the above problems, Japanese Patent Laid-Open Publication No. 2005-064500, No. 2007-027753, and No. 2007-305827 disclose a trench FET (Field Effect Transistor) and a fin FET. Specifically, in the case of the trench FET, a groove is formed in a semiconductor substrate. A gate electrode is formed so as to fill the groove through the gate insulating film. Thus, a three-dimensional channel structure is achieved.
On the other hand, in the case of the fin FET, a silicon fin portion, which functions as a channel, is formed on a semiconductor substrate. Then, a gate electrode is formed so as to cover top and upper-side surfaces of the silicon fin portion. Thus, a three-dimensional channel structure is achieved. In any case, the gate length can be increased, thereby preventing the short channel effect.
Additionally, it has been considered for a DRAM that a recessed gate transistor is used as a selection transistor forming a memory cell. In the case of the recessed gate transistor, a gate electrode (word line) is buried in a surface layer of a semiconductor substrate. In other words, the gate electrode does not protrude from the surface of the semiconductor substrate. Among wires connected to memory cells, only bit liens are positioned over the semiconductor substrate, thereby simplifying arrangement of capacitors, contact plugs, and the like, and enabling easy processing of these elements.
Among the above transistors having the three-dimensional channel structures, there is a transistor including a saddle-fin gate electrode 106, as shown in FIGS. 20 and 21. The saddle-fin gate electrode 106 is formed by: forming recessed gate grooves 103 and 104 in a device isolation region 101 and an active region 102 of a substrate 100, respectively; and forming a conductive material film that fills the grooves 103 and 104 through a gate insulating film 105. Two adjacent active regions 102, between which the gate electrode 106 is formed, include a source region 107a and a drain region 107b (impurity diffusion layers) formed by ion implantation.
However, the width of the groove 103 in the device formation region is reduced along with the reduction in the size of memory cells, thereby increasing the aspect ratio of the groove 103. For this reason, both side surfaces 103a and 103b of the groove 103 have the downwardly narrowing taper shape.
The gate electrode 106 fills the gate grooves 103 and 104 so as to cover the top and upper side surfaces of active regions 102. In this case, the portion of the gate electrode 106, which is in contact with the bottom surface 103c and the tapered side surfaces 103a and 103b of the groove 103, is isolated from the side surface of the active region 102.
Therefore, the side surface of the active region 102 does not function as a channel, and only the upper surface of the active region 102 can function as an effective channel, thereby making it difficult to achieve a sufficient amount of on-current.
FIGS. 22 and 23 illustrate a process flow indicative of a method of manufacturing the above transistor. FIGS. 22A and 23A are plan views. FIGS. 22B and 23B are cross-sectional views taken along line X1-X1′ shown in FIGS. 22A and 23A. FIGS. 22C and 23C are cross-sectional views taken along line X2-X2′ shown in FIGS. 22A and 23A. FIGS. 22D and 23D are cross-sectional views taken along line Y1-Y1′ shown in FIGS. 22A and 23A. FIGS. 22E and 23E are cross-sectional views taken along line Y2-Y2′ shown in FIGS. 22A and 23A. FIGS. 22F and 23F are cross-sectional views taken along line Y3-Y3′ shown in FIGS. 22A and 23A.
Firstly, multiple device isolation grooves 108 are formed in a cell array region SA′ of the substrate 100 including a silicon surface layer. Then, a silicon oxide film 109 is formed so as to fill the grooves 108, as shown in FIG. 22A to 22D. Then, upper surfaces of the substrate 100 and the silicon oxide film 109 are planarized. Thus, the aforementioned device isolation regions 101 and the active regions 102 defined by the device isolation region 101 are formed. The device isolation region 101 and the active region 102 are alternately arranged. At the same time, a groove 108A, which is wider than the device isolation groove 108, is formed in a peripheral region CA′ outside the cell array region SA′. The groove 108A and the device isolation groove 108 have the same depth. The grooves 108 and 108A are filled with the silicon oxide film 109.
Then, a mask layer 110a and a mask layer 110b over the mask layer 110a are formed over the substrate 100. Then, a resist layer (not shown), which has openings at positions corresponding to those of the gate electrodes 106, is formed over the mask layer 110b. Then, the mask layers 110a and 110b are patterned with the resist layer as a mask. Then, the silicon oxide films 109, which fill the grooves 108 and 108A, are selectively removed with the mask layers 110a and 110b. Thus, the recessed gate grooves 103 are formed in the device formation region 101, as shown in FIGS. 23D and 23E.
At this time, both side surfaces 103a and 103b of the groove 103, which are formed in the silicon oxide film 109 in the device formation region 101, have the tapered shape, as shown in FIG. 23C. Additionally, a variation in depth of each groove 103 in the cell array region SA′ is likely to become large. For this reason, the thickness (vertical size) of the silicon oxide film 109 remaining in a bottom portion of each device isolation groove 108 in the cell array region SA′ varies, thereby causing a variation in characteristics of transistors arranged in the cell array region SA′, and therefore causing malfunction of memory cells.
On the other hand, to make the side surfaces 103a and 104b of the groove 103 vertical, the silicon oxide film 109 can be over-etched after the groove 103 is formed. However, it is easier to etch the silicon oxide film 109 in the groove 108A in the peripheral region CA′ than the silicon oxide film 109 in the groove 108 in the cell array region SA′. For this reason, if the silicon oxide film 109 in the cell array region SA′ is further etched, the silicon oxide film 109 in the groove 108A is fully removed, thereby causing the bottom surface of the groove 108A to be exposed. Therefore, the over-etching of the silicon oxide film 109 to make the side surfaces 103a and 103b vertical cannot be carried out.
Although multiple device isolation regions 101 and the active regions 102 are arranged in the cell array region SA′ of an actual transistor, only several device isolation regions 101 and active regions 102 are shown in FIGS. 21A to 23F for simplification.